1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and more particularly, to a duty cycle correction circuit and a semiconductor integrated circuit apparatus including the same.
2. Related Art
In general, a semiconductor integrated circuit such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) improves its operational speed by using both rising and falling edges of clock signals when processing data. Accordingly, unless a ratio of a rising edge interval to a falling edge interval of a clock signal, i.e., a duty ratio, is 50:50, operational efficiency of the integrated circuit is degraded. However, it is difficult for a clock signal used in a semiconductor integrated circuit to have an accurate duty ratio due to various influences, such as a noise, which may exist in the semiconductor integrated circuit. Thus, in order to improve operational efficiency, a semiconductor integrated circuit includes a duty cycle correction circuit to correct a duty ratio of a clock signal.
Commonly, a duty cycle correction circuit is included in a Delay Locked Loop (DLL) circuit to correct a duty cycle of a clock signal pair output from the DLL circuit. However, although it performs a duty cycle correction operation on clock signals at output terminals of the DLL circuit, it causes distorted a duty ratios of clock signals due to delay elements that exist in downstream transmission lines. In addition, when a clock signal pair is transmitted, the transmission line had to be realized as a transmission line pair. Accordingly, area efficiency and power efficiency of a semiconductor integrated circuit are degraded. As a result, the use of a general duty cycle correction circuit in the DLL circuit caused problems, such as signal distortion by a transmission line, area efficiency degradation, and power efficiency degradation.